Fun with FPGAs and CPU Design
I have been hard at work on the Ember CPU design, developing the FPGA hardware implementation in SystemVerilog for the Spartan Edge Accelerator FPGA board. Progress on the ALU implementation is proceeding smoothly. I now have it running in the Vivado Simulator, so the next step is to test it running on hardware.
And, speaking of hardware, I also recently implemented the first display mode to output 80x45 text mode (the image shows 2x scaled font for testing) on a 1280x720 HDMI display. Once we get the CPU up and running, I should be able to run a simple system monitor program on the device.
Stay tuned here, on my hackaday.io project for the gory technical details, or check out the Medium Blog if you are interested in the high-level design process from the beginning. Hope to see you there!